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2005 Microchip Technology Inc.
Preliminary
DS41265A-page 161
PIC16F946
REGISTER 13-5:
EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 18Ch)
R/W-0
U-0
R/W-x
R/W-0
R/S-0
EEPGD
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1
= Accesses program memory
0
= Accesses data memory
bit 6-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1
= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or Brown-out Reset)
0
= The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1
= Allows write cycles
0
= Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
EEPGD = 1:
This bit is ignored
EEPGD = 0:
1
= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be
set, not cleared, in software.)
0
= Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1
= Initiates a memory read (RD is cleared in hardware. The RD bit can only be set, not cleared, in
software.)
0
= Does not initiate an memory read
Legend:
S = Bit can only be set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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